Deliverables
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VHDL source files
- User manual
- Testbench
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Two hours of support included
Site Based License Model
The license allows you to use the core in an unlimited number of projects originating within a 5-mile radius of an address designated as the "licensed site"
Supported FPGA
The HDLC IP Core is pure VHDL, and it is supported on any FPGA
Supported Simulators
All
Campera-ES Communication Solutions
HDLC
The CES HDLC Core is a completely parameterized VHDL IP core able to send and receive serial data in HDLC format full duplex mode with configurable data rates, crc and data encoding
Key Features
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Synthesizable, technology independent VHDL IP Core
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HDLC compatible serial interface controller
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Address filtering, multicast and broadcast
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Receive input FIFO with configurable depth
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Transmit output FIFO with configurable depth
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Supports all standard data rates from 9600 to 921600 baud
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Fully custom data rates also supported – limited only by system
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Receive and transmit interrupt flags
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Receive and transmit FIFO full flags
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NRZ, NRZI with configurable level and Manchester Data Encoding
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Bit Stuffing and Bit Stripping
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Configurable CRC: 16-bit and 32-bit sequence
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Full Dublex
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Optional All Programmable parameters enable run-time reconfigurability
