Radar Library

Deliverables

VHDL source files
User manual
Testbench
Two hours of support included

Site Based License Model

The license allows you to use the core in an unlimited number of projects originating within a 5-mile radius of an address designated as the "licensed site"

Supported FPGA

The HDLC IP Core is pure VHDL, and it is supported on any FPGA

Supported Simulators

All

Campera-ES Communication Solutions

HDLC

The CES HDLC Core is a completely parameterized VHDL IP core able to send and receive serial data in HDLC format full duplex mode with configurable data rates, crc and data encoding

Key Features

Synthesizable, technology independent VHDL IP Core
HDLC compatible serial interface controller
Address filtering, multicast and broadcast
Receive input FIFO with configurable depth
Transmit output FIFO with configurable depth
Supports all standard data rates from 9600 to 921600 baud
Fully custom data rates also supported – limited only by system
Receive and transmit interrupt flags
Receive and transmit FIFO full flags
NRZ, NRZI with configurable level and Manchester Data Encoding
Bit Stuffing and Bit Stripping
Configurable CRC: 16-bit and 32-bit sequence
Full Dublex
Optional All Programmable parameters enable run-time reconfigurability

Datasheet