Simplifying FPGA Complexity

Campera Electronic Systems has more than 10 years of FPGA HDL development experience. More than 20 high performance different designs have been developed and tested on high-end FPGA devices. Our unique mixture of competencies from algorithm design up to HDL and software design guarantees that every single aspect of the customer's design is fully analyzed and that we choose the best solution.

A de-risked, high quality project can be guaranteed through our modern and proprietary HDL development flow, coding standards and tecniques, using stringent design process and proprietary utilities, along with a large and thoroughly verified HDL IP cores building block libraries.

Development of algorithms for complex digital signal processing applications, floating point and bit accurate fixed point models. 

We have developed proprietary algorithms and IP cores for Radar/Sonar, Software Defined Radio, Astronomy, Biomedical and High Performance Computing.

If your next design includes DDC/DUC, Correlators, Pulse compressor, digital filters, FFT/IFFT at the highest rates, our Company is the best partner.

Simulation, documentation and independent assessment of FPGA project requirements.

Our Company can assist customers during the Verification and Validation (V&V) stage with own competences, with proprietary tools, utilities and scripts.

We can assist from the initial V&V definition plan phase, up to documentation and complex simulation.

Independent V&V Partner. 

The Company has developed a mature V&V process, and works in accordance with Safety-Critical standards, like DO-254 and IEC-61508.

FPGA design, certifiable IP cores and V&V for Safety-Critical applications.

Our Company provides services covering the whole design. It means: from requirements definition up to HDL design and FPGA implementation including constraints management, synthesis, routing, test benches and verification.

Customers can easily integrate our vast IP cores library in their design and we will certify the code for your project.

Our Engineers help you obtain more performances, less resource usage, less power, better code standard and overall code improvements.

We have successfully helped our customers to improve the performance of their products without having to re-design the hardware. We improve the maximum frequency for the FPGA or we reduce the resource usage.

The company also provides timing closure services, using proprietary routine analysis tools and a high efficient design metodology 

For an expert point of view or formal code review and to have an high quality code review you can count on our utilities, tools, proprietary scripts, coding standards.

Campera developed a proprietary coding standard and verification scripts that allows to rigourously analyse the reviewed HDL code.

A final comprehensive checklist, with over 100 steps covering the main aspects of VHDL and Verilog design, simulation and implementation, guarantees the best results.

Our Engineers teach advanced engineering training courses. Our Team will introduce you to the most advanced design and verification techniques. 

Scheduled Training Course for 2015

· VHDL 2008

· Assertions

· Tcl scripting for the EDA design flow

High speed digital board design, from design concept to prototype production.

The company has succesfully designed and delivered boards and VHDL control firmware for the most advanced devices, to mention a few:

• SRIO, XAUI, Aurora, 10/40/100GMAC

• High-speed ADCs and DACs (over GSPS)

• Memory controllers: QDR-II/II+, DDR2/3/4, EEPROM

• Complex multi-million gate FPGA/CPLD designs

• Soft and hard embedded microprocessors