HDL Development Flow

CES DESIGN FLOW

HDL code is written to be vendor independent. To allow for maximum compatibility among different EDA tools that customers use we took a conservative, though "conservative" should be considered in a positive meaning, approach.

We design code following IEEE standard 1076-1993 for VHDL (also known as VHDL-93) and IEEE Standard 1364-2001 for Verilog (also known as Verilog 2001).

Each project is defined, architected, developed, verified, released and maintained through a rigorous and efficient process. The process and internal procedures are suitable also to release code in accordance with safety related standards (see note here), such as DO-254 and IEC-61508 to mention a few.

Though this process implies an overhead for us in the development time, allows us to obtain high reliable, mantainable and efficient code.

We called the flow, and related coding standard, CES Design Flow

Key Steps

Architectural design, requirements tracing, Verification and Validation plan definition
Proprietary high efficiency coding standard.
Linting automatic analysis to improve the quality of HDL code. Proprietary utilities and tools for customer support.
Version control system to assure complete track of changes .
RTL level unitary functional test: self-checking with code coverage and requirements tracking.
Modular based design for maximum code reusability.
Standard HDL is used to guarantee vendor and target independence, to ensure full compatibility with hardware and software to simplify maintainability
Logic Synthesis: Tcl script based synthesis management
Verification (Gate Level): Post synthesis simulation compared to RTL level simulation results. If gate level simulations would be too time consuming an alternative approach is used. Formal equivalence check or comparison of two netlist obtained with two different synthesizers
Implementation: Tcl script based implementation managemenVerification (Target level). Hardware tests are used to validate the implementation process. Test vectors used with RTL level simulations are used on the final hardware to validate the final implementation. Customized instrumentations on FPGA allows to inspect internal signals at virtually full speed without using precious internal resource
Documentation: the code and the whole project is fully documented using automatic documentation generator
Manteinace: Bug list traced and appropriately managed